Re: MACH chip question

From: Magnus Kollberg <>
Date: Fri, 12 Jun 1998 09:43:38 +0200


> >I assume these do some bus/address decoding. Does each chip contain
> >different code, or are there 8 of the same to handle all the lines?
> >If they are the same, I could desolder one, copy it, and just piggyback
> >a socket ontop the rest (disabling the power to the smt ones).
> This chip are use to build the 32 bits word from the falcon mother board
> (the 040 haven't dynamic bus sizing) and to recreate some 68000 signals
> from 040 one's. The 3 chip in front of the memeory generate refresh and ram
> adressing.

How do you know all this? Have you axamined the card or have you found the
info somewhere else?

Some time back I talked to an engineer at Wizztronics about the AB040
and their failure the Barracuda. According to him the Falcon needs
a patched TOS to even boot. There a some instruction at boot up which
will make the 040 hang, so it's necessary for the hardware on the
accelerator to decode these instructions and alter them in order
to let the 040 boot at all (make nops out of them). Does anyone have
a comment about this? He claims this was the problem with the Barracuda
and they could not release it as it needed a patched TOS to even
boot. We all know that TOS 4.01 and possible 4.02 doesn't boot, so
there must be something at boot up which goes wrong. I find it a bit
hard to belive that the AB040 would decode instructions at bootup
and alter them though.

As the AB040 hasn't got the fastest RAM access in the world, maybe it
would be possible to change these 3 PLDs and make it faster. If someone
just could get hold of those damned equations for the PLDs. It could be
a interresting project for someone who has got lots of spare time...

Also, do you happen to know anything about the expantion bus on the
AB040? Is it just a plain CPU bus from the 040? Pinning?

//Magnus Kollberg
Received on ma. juni 15 1998 - 00:15:00 CEST

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