040/snoop/MI/timing on AB

From: Michael Grove <mgrove_at_iwvisp.com>
Date: Fri, 26 Mar 1999 08:21:10 -0800

More info...

My A/B has a socket installed for the 040, and I use an
adapter to mate the 040 CPU or 060 adapter/CPU to the A/B.

The A/B holds SC0 line low and SC1 line HI continually as
far as I can tell.

I removed both pins (SC0 and SC1) with the 040 installed and
this made no difference in operation from TOS or
diagnostics. The snoop lines go to the MACH chip closest to
the CPU. (SC0,SC1 LOW).

I removed the MI (memory inhibit) pin from the 040 socket.
The 040 would not boot from TOS, but would get almost to
displaying a partial red FUJI. (MI LOW-asserted).

With the MI pin removed, diagnostics worked just like the
060 was installed. The 040 would fail the DMA SCSI and
Floppy test, and fail the same video timing test the 060 is
having problems with. The MI line goes to the MACH chip
closest to the motherboard ribbon connector on the A/B (far
left). (MI LOW-asserted). Other diagnostic test performed

b) I changed the dram wait state setting on the motherboard
from 1 wait state to 0 wait state. Under diagnostics, with
the MI pin enabled and 040 installed, the same video timing
test would fail.
(MI status dependent on 040 CPU)

d) I found a Motorola data sheet that addresses interfacing
a 68060 with a 68360. It says that the 68060 can negate the
TS signal as quickly as 3nSec from the rising edge of S1 (on
the 68360, this is out of specification, as well as out of
specification for the 68040 design, so the MACH chips, or
COMBEL may have problems with this too). To correct this
problem, the user must shift the window of TS low. this can
be achieved by introducing a delay in TS from the 68060 to
the 68360. One example is to place two FAST logic devices
back to back. The total delay throughout the two is 4.4nSec
min to 13.3nSec max. this delay is enough to correct the
problem without causing a specification violation on TS

f) It appears that the AB is latching onto the MI signal. If
MI is asserted (MI LOW) TA and TEA are ignored. MI negated
(MI HI) the bus master is allowed to proceed (from the 040
users manual. MI status dependent on 040 CPU).

Changing dram to 0 wait state causes the same memory counter
error in diagnostics, and will not allow the machine to boot
from TOS, the same as if the 060 was installed. (MI status
dependent on 040 CPU).

It seems that there is a timing error somewhere here. Maybe
the COMBEL needs TS asserted for a longer period for video
timing. The field service manual does not get that involved
into chip specifics.

Sense TS is an I/O line, will installing two fast logic
devices in the manner explained above affect TS signals
traveling through the 74AC04's to the 040, or is the signal
not delayed going backward through the circuit?

What were the designers thinking when they utilized an
output for other than what it was intended for??????? :(.

Received on ti. april 06 1999 - 21:37:54 CEST

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